
module frontend_test #(
    parameter FRONTEND_WIDTH = 2
) (
    input clk,
    input rst,
    // Redirect Req by backend
    input i_redirect_valid,
    input word_t i_redirect_pc,
    input BranchType i_redirect_bpu_res_branch_type,
    input i_redirect_bpu_res_taken,
    input [`WORD_BITS-1:0] i_redirect_bpu_res_target,
    input i_redirect_bpu_res_ras_valid,
    input [`RAS_AW-1:0] i_redirect_bpu_res_ras_pointer,
    input [`WORD_BITS-1:0] i_redirect_bpu_res_ras_top,
    input [1:0] i_redirect_bpu_res_bi_cnt,
    // IRAM Req
    input o_iram_ready,
    output o_iram_valid,
    output IRAM_Req o_iram_req,
    // IRAM Rsp
    input IRAM_Rsp i_iram_rsp,
    // IBUF
    output o_ibuf_valid,
    input o_ibuf_ready,
    output o_ibuf_entry_valid[FRONTEND_WIDTH-1:0],
    output [`WORD_BITS-1:0] o_ibuf_entry_pc[FRONTEND_WIDTH-1:0],
    output [31:0] o_ibuf_entry_inst[FRONTEND_WIDTH-1:0],
    output o_ibuf_entry_bpu_res_valid[FRONTEND_WIDTH-1:0],

    output BranchType o_ibuf_entry_bpu_res_branch_type[FRONTEND_WIDTH-1:0],
    output o_ibuf_entry_bpu_res_taken[FRONTEND_WIDTH-1:0],
    output [`WORD_BITS-1:0] o_ibuf_entry_bpu_res_target[FRONTEND_WIDTH-1:0],
    output o_ibuf_entry_bpu_res_ras_valid[FRONTEND_WIDTH-1:0],
    output [`RAS_AW-1:0] o_ibuf_entry_bpu_res_ras_pointer[FRONTEND_WIDTH-1:0],
    output [`WORD_BITS-1:0] o_ibuf_entry_bpu_res_ras_top[FRONTEND_WIDTH-1:0],
    output [1:0] o_ibuf_entry_bpu_res_bi_cnt[FRONTEND_WIDTH-1:0],
    //for performace
    output ibuf_full,
    output ibuf_empty
);
  BPU_Res i_redirect_bpu_res;
  assign i_redirect_bpu_res.branch_type = i_redirect_bpu_res_branch_type;
  assign i_redirect_bpu_res.taken = i_redirect_bpu_res_taken;
  assign i_redirect_bpu_res.target = i_redirect_bpu_res_target;
  assign i_redirect_bpu_res.ras_valid = i_redirect_bpu_res_ras_valid;
  assign i_redirect_bpu_res.ras_pointer = i_redirect_bpu_res_ras_pointer;
  assign i_redirect_bpu_res.ras_top = i_redirect_bpu_res_ras_top;
  assign i_redirect_bpu_res.bi_cnt = i_redirect_bpu_res_bi_cnt;
  IBUF_Entry o_ibuf_entry[FRONTEND_WIDTH-1:0];


  BPU_Res o_ibuf_entry_bpu_res[FRONTEND_WIDTH-1:0];
  genvar i;
  generate
    for (i = 0; i < FRONTEND_WIDTH; i = i + 1) begin
      assign o_ibuf_entry_pc[i] = o_ibuf_entry[i].pc;
      assign o_ibuf_entry_inst[i] = o_ibuf_entry[i].inst;
      assign o_ibuf_entry_bpu_res[i] = o_ibuf_entry[i].bpu_res;
      assign o_ibuf_entry_bpu_res_valid[i] = o_ibuf_entry[i].bpu_res_valid;

      assign o_ibuf_entry_bpu_res_branch_type[i] = o_ibuf_entry_bpu_res[i].branch_type;
      assign o_ibuf_entry_bpu_res_taken[i] = o_ibuf_entry_bpu_res[i].taken;
      assign o_ibuf_entry_bpu_res_target[i] = o_ibuf_entry_bpu_res[i].target;
      assign o_ibuf_entry_bpu_res_ras_valid[i] = o_ibuf_entry_bpu_res[i].ras_valid;
      assign o_ibuf_entry_bpu_res_ras_pointer[i] = o_ibuf_entry_bpu_res[i].ras_pointer;
      assign o_ibuf_entry_bpu_res_ras_top[i] = o_ibuf_entry_bpu_res[i].ras_top;
      assign o_ibuf_entry_bpu_res_bi_cnt[i] = o_ibuf_entry_bpu_res[i].bi_cnt;

    end
  endgenerate


  frontend #(FRONTEND_WIDTH) inst_frontend (.*);
endmodule
